Eric Panning

Eric Panning

Engineering Manager, Intel Corp

Eric Panning is a Patterning Technologist within Intel’s Supplier Technology and Industry Development organization. His focus is all aspects of advanced patterning solutions including tool and material development as well as industry and government partnerships. He is the Intel driver behind the EUREKA program with the Center for X-ray Optics at Lawrence Berkeley National Labs for advanced EUV lithography.

Eric’s career in patterning spans 20+ years in multiple orgs and a full range of technologies include 248nm, 193nm, immersion, high NA immersion, 157nm and EUV lithography. Eric is a SPIE Senior Member and conference chair of the Novel Patterning Conference at SPIE Advanced Lithography as well as the US Program Chair for the ongoing SPIE EUV Symposium.

Eric is also experienced in process virtualization to improve process integration technical performance and cycle time. He holds 7 patents in the patterning field

Eric’s educational background covers multiple disciplines including semiconductor devices, bio engineering and aerospace. Eric holds a M.S and B.S in Electrical Engineering from the Georgia Institute of Technology. While attending college he was also employed by the Aerospace Corporation in El Segundo CA working on arc jet and ion engine technologies for satellite station keeping for commercial and DOD Space and Missile Command applications.